Computer System Architecture
180 live simulations - number systems, Boolean algebra, digital logic, CPU organization, assembly programming, I/O and memory hierarchy.
180 simulators found.
Number System Introduction
Number System Introduction - live Computer System Architecture simulation (Number Systems).
Decimal Number System — Place Value
Decimal Number System — Place Value - live Computer System Architecture simulation (Number Systems).
Binary Number System — Powers of 2
Binary Number System — Powers of 2 - live Computer System Architecture simulation (Number Systems).
Octal Number System
Octal Number System - live Computer System Architecture simulation (Number Systems).
Hexadecimal Number System
Hexadecimal Number System - live Computer System Architecture simulation (Number Systems).
Decimal to Binary — Repeated Division by 2
Decimal to Binary — Repeated Division by 2 - live Computer System Architecture simulation (Number Systems).
Binary to Decimal — Sum of Powers
Binary to Decimal — Sum of Powers - live Computer System Architecture simulation (Number Systems).
Decimal to Octal — Division by 8
Decimal to Octal — Division by 8 - live Computer System Architecture simulation (Number Systems).
Octal to Decimal — Place Value
Octal to Decimal — Place Value - live Computer System Architecture simulation (Number Systems).
Decimal to Hexadecimal — Division by 16
Decimal to Hexadecimal — Division by 16 - live Computer System Architecture simulation (Number Systems).
Hexadecimal to Decimal
Hexadecimal to Decimal - live Computer System Architecture simulation (Number Systems).
Binary to Octal — 3-bit Grouping
Binary to Octal — 3-bit Grouping - live Computer System Architecture simulation (Number Systems).
Binary to Hexadecimal — 4-bit Grouping
Binary to Hexadecimal — 4-bit Grouping - live Computer System Architecture simulation (Number Systems).
Octal to Binary
Octal to Binary - live Computer System Architecture simulation (Number Systems).
Hexadecimal to Binary
Hexadecimal to Binary - live Computer System Architecture simulation (Number Systems).
Weighted Binary Codes — 8421 BCD
Weighted Binary Codes — 8421 BCD - live Computer System Architecture simulation (Number Systems).
Non-Weighted Codes — Excess-3 & Gray
Non-Weighted Codes — Excess-3 & Gray - live Computer System Architecture simulation (Number Systems).
Alphanumeric Codes — ASCII
Alphanumeric Codes — ASCII - live Computer System Architecture simulation (Number Systems).
Error Detection Codes — Parity
Error Detection Codes — Parity - live Computer System Architecture simulation (Number Systems).
Error Correction Codes — Hamming
Error Correction Codes — Hamming - live Computer System Architecture simulation (Number Systems).
Boolean Logic Introduction
Boolean Logic Introduction - live Computer System Architecture simulation (Boolean Algebra).
Boolean Variables
Boolean Variables - live Computer System Architecture simulation (Boolean Algebra).
AND Operation
AND Operation - live Computer System Architecture simulation (Boolean Algebra).
OR Operation
OR Operation - live Computer System Architecture simulation (Boolean Algebra).
NOT Operation
NOT Operation - live Computer System Architecture simulation (Boolean Algebra).
NAND Operation
NAND Operation - live Computer System Architecture simulation (Boolean Algebra).
NOR Operation
NOR Operation - live Computer System Architecture simulation (Boolean Algebra).
XOR Operation
XOR Operation - live Computer System Architecture simulation (Boolean Algebra).
XNOR Operation
XNOR Operation - live Computer System Architecture simulation (Boolean Algebra).
Operator Precedence
Operator Precedence - live Computer System Architecture simulation (Boolean Algebra).
Boolean Laws
Boolean Laws - live Computer System Architecture simulation (Boolean Algebra).
De Morgan's Theorem
De Morgan's Theorem - live Computer System Architecture simulation (Boolean Algebra).
Boolean Function Representation
Boolean Function Representation - live Computer System Architecture simulation (Boolean Algebra).
Sum of Products (SOP)
Sum of Products (SOP) - live Computer System Architecture simulation (Boolean Algebra).
Product of Sums (POS)
Product of Sums (POS) - live Computer System Architecture simulation (Boolean Algebra).
Digital Computer Basics
Digital Computer Basics - live Computer System Architecture simulation (Digital Logic Circuits).
Logic Gate Symbols
Logic Gate Symbols - live Computer System Architecture simulation (Digital Logic Circuits).
Gate Truth Tables
Gate Truth Tables - live Computer System Architecture simulation (Digital Logic Circuits).
Universal Gates
Universal Gates - live Computer System Architecture simulation (Digital Logic Circuits).
Boolean Expression to Logic Circuit
Boolean Expression to Logic Circuit - live Computer System Architecture simulation (Digital Logic Circuits).
Logic Circuit to Boolean Expression
Logic Circuit to Boolean Expression - live Computer System Architecture simulation (Digital Logic Circuits).
K-Map Introduction
K-Map Introduction - live Computer System Architecture simulation (Digital Logic Circuits).
2-Variable K-Map
2-Variable K-Map - live Computer System Architecture simulation (Digital Logic Circuits).
3-Variable K-Map
3-Variable K-Map - live Computer System Architecture simulation (Digital Logic Circuits).
4-Variable K-Map
4-Variable K-Map - live Computer System Architecture simulation (Digital Logic Circuits).
Don't Care Conditions
Don't Care Conditions - live Computer System Architecture simulation (Digital Logic Circuits).
Combinational Circuit Meaning
Combinational Circuit Meaning - live Computer System Architecture simulation (Digital Logic Circuits).
Half Adder
Half Adder - live Computer System Architecture simulation (Digital Logic Circuits).
Full Adder
Full Adder - live Computer System Architecture simulation (Digital Logic Circuits).
Half Subtractor
Half Subtractor - live Computer System Architecture simulation (Digital Logic Circuits).
Full Subtractor
Full Subtractor - live Computer System Architecture simulation (Digital Logic Circuits).
Parallel Binary Adder
Parallel Binary Adder - live Computer System Architecture simulation (Digital Logic Circuits).
Encoder
Encoder - live Computer System Architecture simulation (Digital Logic Circuits).
Decoder
Decoder - live Computer System Architecture simulation (Digital Logic Circuits).
2-to-4 Decoder
2-to-4 Decoder - live Computer System Architecture simulation (Digital Logic Circuits).
3-to-8 Decoder
3-to-8 Decoder - live Computer System Architecture simulation (Digital Logic Circuits).
Multiplexer
Multiplexer - live Computer System Architecture simulation (Digital Logic Circuits).
4-to-1 MUX
4-to-1 MUX - live Computer System Architecture simulation (Digital Logic Circuits).
Demultiplexer
Demultiplexer - live Computer System Architecture simulation (Digital Logic Circuits).
Sequential Circuit Meaning
Sequential Circuit Meaning - live Computer System Architecture simulation (Digital Logic Circuits).
Latch Introduction
Latch Introduction - live Computer System Architecture simulation (Digital Logic Circuits).
SR Flip-Flop
SR Flip-Flop - live Computer System Architecture simulation (Digital Logic Circuits).
JK Flip-Flop
JK Flip-Flop - live Computer System Architecture simulation (Digital Logic Circuits).
D Flip-Flop
D Flip-Flop - live Computer System Architecture simulation (Digital Logic Circuits).
T Flip-Flop
T Flip-Flop - live Computer System Architecture simulation (Digital Logic Circuits).
Clock Pulse
Clock Pulse - live Computer System Architecture simulation (Digital Logic Circuits).
Integrated Circuits — SSI to VLSI
Integrated Circuits — SSI to VLSI - live Computer System Architecture simulation (Digital Logic Circuits).
Register — Meaning
Register — Meaning - live Computer System Architecture simulation (Digital Logic Circuits).
Shift Register
Shift Register - live Computer System Architecture simulation (Digital Logic Circuits).
Counter — Meaning
Counter — Meaning - live Computer System Architecture simulation (Digital Logic Circuits).
Asynchronous (Ripple) Counter
Asynchronous (Ripple) Counter - live Computer System Architecture simulation (Digital Logic Circuits).
Synchronous Counter
Synchronous Counter - live Computer System Architecture simulation (Digital Logic Circuits).
Memory Unit Basics
Memory Unit Basics - live Computer System Architecture simulation (Digital Logic Circuits).
RAM and ROM
RAM and ROM - live Computer System Architecture simulation (Digital Logic Circuits).
Digital Logic Revision
Digital Logic Revision - live Computer System Architecture simulation (Digital Logic Circuits).
Stored Program Concept
Stored Program Concept - live Computer System Architecture simulation (Basic Computer Organization).
Basic Computer Block Diagram
Basic Computer Block Diagram - live Computer System Architecture simulation (Basic Computer Organization).
Bus System
Bus System - live Computer System Architecture simulation (Basic Computer Organization).
Instruction Code Meaning
Instruction Code Meaning - live Computer System Architecture simulation (Basic Computer Organization).
Instruction Format
Instruction Format - live Computer System Architecture simulation (Basic Computer Organization).
Computer Registers
Computer Registers - live Computer System Architecture simulation (Basic Computer Organization).
Address Register (AR)
Address Register (AR) - live Computer System Architecture simulation (Basic Computer Organization).
Program Counter (PC)
Program Counter (PC) - live Computer System Architecture simulation (Basic Computer Organization).
Data Register (DR)
Data Register (DR) - live Computer System Architecture simulation (Basic Computer Organization).
Accumulator (AC)
Accumulator (AC) - live Computer System Architecture simulation (Basic Computer Organization).
Instruction Register (IR)
Instruction Register (IR) - live Computer System Architecture simulation (Basic Computer Organization).
Control Unit
Control Unit - live Computer System Architecture simulation (Basic Computer Organization).
Timing Signals
Timing Signals - live Computer System Architecture simulation (Basic Computer Organization).
Fetch Cycle
Fetch Cycle - live Computer System Architecture simulation (Basic Computer Organization).
Decode Cycle
Decode Cycle - live Computer System Architecture simulation (Basic Computer Organization).
Execute Cycle
Execute Cycle - live Computer System Architecture simulation (Basic Computer Organization).
Instruction Cycle — Complete
Instruction Cycle — Complete - live Computer System Architecture simulation (Basic Computer Organization).
Register-Reference Instructions
Register-Reference Instructions - live Computer System Architecture simulation (Basic Computer Organization).
Memory-Reference Instructions
Memory-Reference Instructions - live Computer System Architecture simulation (Basic Computer Organization).
Direct Addressing
Direct Addressing - live Computer System Architecture simulation (Basic Computer Organization).
Indirect Addressing
Indirect Addressing - live Computer System Architecture simulation (Basic Computer Organization).
Input Instruction (INP)
Input Instruction (INP) - live Computer System Architecture simulation (Basic Computer Organization).
Output Instruction (OUT)
Output Instruction (OUT) - live Computer System Architecture simulation (Basic Computer Organization).
Interrupt — Meaning
Interrupt — Meaning - live Computer System Architecture simulation (Basic Computer Organization).
Interrupt Cycle
Interrupt Cycle - live Computer System Architecture simulation (Basic Computer Organization).
Control Memory Concept
Control Memory Concept - live Computer System Architecture simulation (Basic Computer Organization).
Hardwired Control
Hardwired Control - live Computer System Architecture simulation (Basic Computer Organization).
Microprogrammed Control
Microprogrammed Control - live Computer System Architecture simulation (Basic Computer Organization).
Basic Computer Data Flow
Basic Computer Data Flow - live Computer System Architecture simulation (Basic Computer Organization).
Organization Revision
Organization Revision - live Computer System Architecture simulation (Basic Computer Organization).
Machine Language
Machine Language - live Computer System Architecture simulation (Programming the Basic Computer).
Assembly Language
Assembly Language - live Computer System Architecture simulation (Programming the Basic Computer).
Assembler — Meaning
Assembler — Meaning - live Computer System Architecture simulation (Programming the Basic Computer).
Assembly Instruction Format
Assembly Instruction Format - live Computer System Architecture simulation (Programming the Basic Computer).
Basic Computer Program Entry
Basic Computer Program Entry - live Computer System Architecture simulation (Programming the Basic Computer).
Load and Store Program
Load and Store Program - live Computer System Architecture simulation (Programming the Basic Computer).
Addition Program
Addition Program - live Computer System Architecture simulation (Programming the Basic Computer).
Subtraction Program (2's Complement)
Subtraction Program (2's Complement) - live Computer System Architecture simulation (Programming the Basic Computer).
Program Loop
Program Loop - live Computer System Architecture simulation (Programming the Basic Computer).
Conditional Branch
Conditional Branch - live Computer System Architecture simulation (Programming the Basic Computer).
Unconditional Branch (BUN)
Unconditional Branch (BUN) - live Computer System Architecture simulation (Programming the Basic Computer).
Subroutine — Meaning
Subroutine — Meaning - live Computer System Architecture simulation (Programming the Basic Computer).
BSA Instruction
BSA Instruction - live Computer System Architecture simulation (Programming the Basic Computer).
Input Programming
Input Programming - live Computer System Architecture simulation (Programming the Basic Computer).
Output Programming
Output Programming - live Computer System Architecture simulation (Programming the Basic Computer).
CPU Introduction
CPU Introduction - live Computer System Architecture simulation (Central Processing Unit).
General Register Organization
General Register Organization - live Computer System Architecture simulation (Central Processing Unit).
Register Transfer
Register Transfer - live Computer System Architecture simulation (Central Processing Unit).
ALU Operations
ALU Operations - live Computer System Architecture simulation (Central Processing Unit).
Control Word
Control Word - live Computer System Architecture simulation (Central Processing Unit).
Stack Organization
Stack Organization - live Computer System Architecture simulation (Central Processing Unit).
Stack Pointer (SP)
Stack Pointer (SP) - live Computer System Architecture simulation (Central Processing Unit).
Reverse Polish Notation (RPN)
Reverse Polish Notation (RPN) - live Computer System Architecture simulation (Central Processing Unit).
Instruction Format — Fields
Instruction Format — Fields - live Computer System Architecture simulation (Central Processing Unit).
Zero-Address Instruction
Zero-Address Instruction - live Computer System Architecture simulation (Central Processing Unit).
One-Address Instruction
One-Address Instruction - live Computer System Architecture simulation (Central Processing Unit).
Two-Address Instruction
Two-Address Instruction - live Computer System Architecture simulation (Central Processing Unit).
Three-Address Instruction
Three-Address Instruction - live Computer System Architecture simulation (Central Processing Unit).
Addressing Mode Introduction
Addressing Mode Introduction - live Computer System Architecture simulation (Central Processing Unit).
Immediate Addressing
Immediate Addressing - live Computer System Architecture simulation (Central Processing Unit).
Direct Addressing
Direct Addressing - live Computer System Architecture simulation (Central Processing Unit).
Indirect Addressing
Indirect Addressing - live Computer System Architecture simulation (Central Processing Unit).
Register Addressing
Register Addressing - live Computer System Architecture simulation (Central Processing Unit).
RISC Computer
RISC Computer - live Computer System Architecture simulation (Central Processing Unit).
CISC Computer
CISC Computer - live Computer System Architecture simulation (Central Processing Unit).
Peripheral Devices
Peripheral Devices - live Computer System Architecture simulation (Input-Output Organization).
I/O Interface
I/O Interface - live Computer System Architecture simulation (Input-Output Organization).
I/O Bus and Interface Modules
I/O Bus and Interface Modules - live Computer System Architecture simulation (Input-Output Organization).
Asynchronous Data Transfer
Asynchronous Data Transfer - live Computer System Architecture simulation (Input-Output Organization).
Strobe Control
Strobe Control - live Computer System Architecture simulation (Input-Output Organization).
Handshaking Method
Handshaking Method - live Computer System Architecture simulation (Input-Output Organization).
Programmed I/O
Programmed I/O - live Computer System Architecture simulation (Input-Output Organization).
Interrupt-Initiated I/O
Interrupt-Initiated I/O - live Computer System Architecture simulation (Input-Output Organization).
Direct Memory Access (DMA)
Direct Memory Access (DMA) - live Computer System Architecture simulation (Input-Output Organization).
DMA Controller
DMA Controller - live Computer System Architecture simulation (Input-Output Organization).
Priority Interrupt
Priority Interrupt - live Computer System Architecture simulation (Input-Output Organization).
Daisy Chaining
Daisy Chaining - live Computer System Architecture simulation (Input-Output Organization).
Parallel Priority Interrupt
Parallel Priority Interrupt - live Computer System Architecture simulation (Input-Output Organization).
Serial Communication
Serial Communication - live Computer System Architecture simulation (Input-Output Organization).
I/O Revision — Comparison
I/O Revision — Comparison - live Computer System Architecture simulation (Input-Output Organization).
Memory Hierarchy Introduction
Memory Hierarchy Introduction - live Computer System Architecture simulation (Memory Hierarchy).
Memory Access Time
Memory Access Time - live Computer System Architecture simulation (Memory Hierarchy).
Main Memory (RAM)
Main Memory (RAM) - live Computer System Architecture simulation (Memory Hierarchy).
RAM Types — SRAM vs DRAM
RAM Types — SRAM vs DRAM - live Computer System Architecture simulation (Memory Hierarchy).
ROM Types — PROM, EPROM, EEPROM
ROM Types — PROM, EPROM, EEPROM - live Computer System Architecture simulation (Memory Hierarchy).
Auxiliary Memory
Auxiliary Memory - live Computer System Architecture simulation (Memory Hierarchy).
Magnetic Disk Organization
Magnetic Disk Organization - live Computer System Architecture simulation (Memory Hierarchy).
Associative Memory (CAM)
Associative Memory (CAM) - live Computer System Architecture simulation (Memory Hierarchy).
Cache Memory — Meaning
Cache Memory — Meaning - live Computer System Architecture simulation (Memory Hierarchy).
Cache Hit
Cache Hit - live Computer System Architecture simulation (Memory Hierarchy).
Cache Miss
Cache Miss - live Computer System Architecture simulation (Memory Hierarchy).
Direct Mapping
Direct Mapping - live Computer System Architecture simulation (Memory Hierarchy).
Associative Mapping
Associative Mapping - live Computer System Architecture simulation (Memory Hierarchy).
Set-Associative Mapping
Set-Associative Mapping - live Computer System Architecture simulation (Memory Hierarchy).
Cache Replacement
Cache Replacement - live Computer System Architecture simulation (Memory Hierarchy).
Write-Through
Write-Through - live Computer System Architecture simulation (Memory Hierarchy).
Write-Back
Write-Back - live Computer System Architecture simulation (Memory Hierarchy).
Virtual Memory
Virtual Memory - live Computer System Architecture simulation (Memory Hierarchy).
Paging
Paging - live Computer System Architecture simulation (Memory Hierarchy).
Page Table — Address Translation
Page Table — Address Translation - live Computer System Architecture simulation (Memory Hierarchy).
Page Fault
Page Fault - live Computer System Architecture simulation (Memory Hierarchy).
TLB — Translation Lookaside Buffer
TLB — Translation Lookaside Buffer - live Computer System Architecture simulation (Memory Hierarchy).
Memory Management Hardware (MMU)
Memory Management Hardware (MMU) - live Computer System Architecture simulation (Memory Hierarchy).
Memory Hierarchy Comparison
Memory Hierarchy Comparison - live Computer System Architecture simulation (Memory Hierarchy).
Final Memory Revision
Final Memory Revision - live Computer System Architecture simulation (Memory Hierarchy).